{"id":12747,"date":"2026-09-17T11:35:37","date_gmt":"2026-09-17T11:35:37","guid":{"rendered":"https:\/\/geyuanelectronics.com\/?p=12747"},"modified":"2026-09-17T11:39:25","modified_gmt":"2026-09-17T11:39:25","slug":"atraves-de-tecnicas-de-concecao-no-desenho-de-placas-de-circuito-impresso","status":"publish","type":"post","link":"https:\/\/geyuanelectronics.com\/pt\/via-design-techniques-in-pcb-design\/","title":{"rendered":"T\u00e9cnicas de Design na Concep\u00e7\u00e3o de PCB"},"content":{"rendered":"<nav aria-label=\"breadcrumbs\" class=\"rank-math-breadcrumb\"><p><span class=\"last\">Home<\/span><\/p><\/nav>\n\n\n\n<h1 class=\"wp-block-heading has-x-large-font-size\"><strong>Via Design Techniques in PCB Design<\/strong><strong><\/strong><\/h1>\n\n\n\n<p class=\"wp-block-paragraph\">In <a href=\"https:\/\/geyuanelectronics.com\/capabilities\/circuit-design\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/capabilities\/circuit-design\/\">PCB design<\/a>, via design is a crucial factor. It consists of the hole, the surrounding pad area, and the POWER layer isolation area, and is generally classified into three types: blind vias, buried vias, and through-hole vias. The engineering team at <a href=\"https:\/\/geyuanelectronics.com\/about\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/about\/\">Geyuan Electronics<\/a>, through analysis of parasitic capacitance and inductance in vias during the PCB design process, has summarized some key considerations and related design techniques for PCB via design. Currently, PCB design is widely used in fields such as communications, computers, and graphics processing. All high-tech, high-value-added electronic product designs strive for low power consumption, low electromagnetic radiation, high reliability, miniaturization, and lightweight characteristics. To achieve these goals, via design is a vital factor in PCB design.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Basic Components and Technical Specifications of PCB Vias<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Vias are a crucial element in multilayer PCB design. A via primarily consists of three parts: the hole itself, the surrounding pad area, and the power layer isolation area. The via manufacturing process involves chemically depositing a metal layer onto the cylindrical surface of the via wall to connect the copper foils in the intermediate layers. The top and bottom surfaces of the via are shaped like ordinary pads, which can be directly connected to the traces on the top and bottom surfaces, or left unconnected. Vias serve to provide electrical connections and to fix or position components.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Classification of vias<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Vias are generally classified into three categories: blind holes, buried holes, and through holes.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><td><strong>blind hole<\/strong><strong><\/strong><\/td><td>Blind vias are located on the top and bottom surfaces of printed circuit boards, have a certain depth, and are used to connect surface circuits to underlying inner circuits. The depth and diameter of the via typically do not exceed a certain ratio.<\/td><\/tr><tr><td><strong>Buried Hole<\/strong><strong><\/strong><\/td><td>Buried vias are connection holes located on the inner layer of a printed circuit board that do not extend to the surface of the board.<\/td><\/tr><tr><td><strong>Through hole<\/strong><strong><\/strong><\/td><td>Through-holes are holes that pass through the entire circuit board and can be used to achieve internal interconnections or as mounting holes for components. Because through-holes are easier to manufacture and less expensive, they are commonly used in printed circuit boards.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>PCB via design analysis<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Both blind vias and buried vias are located on the inner layers of a circuit board. They are formed using a through-hole molding process before lamination, and several inner layers may be overlapped during the via formation process. Because through-holes are easier to implement and have lower costs, they are used in the vast majority of printed circuit boards instead of the other two types of vias. Unless otherwise specified, the vias mentioned below are considered as through-holes.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">From a PCB design perspective, a via mainly consists of two parts: the drill hole in the center and the pad area surrounding the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always prefer vias to be as small as possible, allowing for more routing space on the board. Furthermore, smaller vias have lower parasitic capacitance, making them more suitable for high-speed circuits. However, reducing the via size also increases cost, and the size cannot be reduced indefinitely. It is limited by drilling and plating processes: smaller holes require longer drilling times and are more prone to centering; and when the hole depth exceeds six times the drill diameter, uniform copper plating on the hole walls cannot be guaranteed. For example, the thickness (through-hole depth) of a typical 6-layer PCB is around 50 mil, so PCB manufacturers can only provide drill diameters as small as 8 mil.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Parasitic capacitance of vias<\/strong><strong><\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Vias themselves have parasitic capacitance to ground. If the diameter of the via on the ground plane is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the substrate is \u03b5, then the parasitic capacitance of the via is approximately: C = 1.41\u03b5TD1\/(D2-D1). The main effect of the parasitic capacitance of vias on the circuit is to prolong the signal rise time and reduce the circuit speed. For example, for a 50-mil thick PCB board, if a via with an inner diameter of 10 mil and a pad diameter of 20 mil is used, and the distance between the pad and the ground copper area is 32 mil, then we can approximate the parasitic capacitance of the via using the formula above: C = 1.41 x 4.4 x 0.050 x 0.020 \/ (0.032 &#8211; 0.020) = 0.517 pF. The change in rise time caused by this capacitance is: T10 &#8211; 90 = 2.2C(Z0\/2) = 2.2 x 0.517 x (55\/2) = 31.28 ps. From these values, it can be seen that although the effect of the reduced rise time caused by the parasitic capacitance of a single via is not very significant, designers should still carefully consider the use of vias for layer switching multiple times in the routing.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>How to calculate parasitic capacitance?<\/strong><strong><\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">The via itself has parasitic capacitance to ground. If the diameter of the via&#8217;s isolation hole on the ground plane is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the substrate is \u03b5, then the size of the via&#8217;s parasitic capacitance is approximately:<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>C = K * \u03b50 * 3.14 * TD1 \/ (D2 &#8211; D1)<\/strong><strong><\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Where \u03b50 is the vacuum permittivity, and K is the relative (vacuum \u03b50) permittivity of the PCB.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Parasitic inductance of vias<\/strong><strong><\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Vias possess both parasitic capacitance and parasitic inductance. In high-speed digital circuit design, the harmful effects of via parasitic inductance often outweigh those of parasitic capacitance. Its parasitic series inductance weakens the contribution of bypass capacitors, reducing the filtering effectiveness of the entire power supply system. We can use the following formula to roughly calculate the approximate parasitic inductance of a via: L = 5.08h[ln(4h\/d) + 1] where L is the via inductance, h is the via length, and d is the diameter of the center drill hole. It can be seen from the formula that the via diameter has a relatively small impact on the inductance, while the via length has the greatest impact. Using the example above, the via inductance can be calculated as: L = 5.08 x 0.050[ln(4 x 0.050\/0.010) + 1] = 1.015nH. If the signal rise time is 1ns, then its equivalent impedance is: XL = \u03c0L\/T10 &#8211; 90 = 3.19\u03a9. Such impedance cannot be ignored when high-frequency current passes through it. Special attention should be paid to the fact that when the bypass capacitor is connected to the power plane and the ground plane, it needs to pass through two vias, which will multiply the parasitic inductance of the vias.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>How to calculate parasitic inductance?<\/strong><strong><\/strong><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Similarly, vias possess both parasitic capacitance and parasitic inductance. In high-speed digital circuit design, the harmful effects of via parasitic inductance often outweigh the impact of parasitic capacitance. Its parasitic series inductance weakens the contribution of bypass capacitors, thus reducing the filtering effectiveness of the entire power supply system.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">We can easily calculate the parasitic inductance of a via using the following formula:<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>L = 5.08h[ln(4h\/d) + 1]<\/strong><strong><\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>L refers to the inductance of the via.<\/strong><strong><\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>h is the length of the via.<\/strong><strong><\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>d is the diameter of the center borehole.<\/strong><strong><\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">As can be seen from the formula, the diameter of the via has a relatively small impact on the inductance, while the length of the via has the greatest impact on the inductance. The parasitic capacitance of the via mainly affects the circuit by prolonging the signal rise time and reducing the circuit speed.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>PCB via design<\/strong> <strong>techniques<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Through the above analysis of the parasitic characteristics of vias, we can see that in PCB design, seemingly simple vias can often bring significant negative effects to the circuit design. To reduce the adverse effects of via parasitic effects, the following should be considered during the design process:<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(1) Select a reasonable via size. For multilayer PCB designs with general density, vias of 0.25mm\/0.51mm\/0.91mm (drill hole\/pad\/POWER isolation area) are preferred; for some high-density PCBs, vias of 0.20mm\/0.46mm\/0.86mm can also be used, or non-through-hole vias can be tried; for power or ground vias, larger sizes can be considered to reduce impedance;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(2) The larger the POWER isolation area, the better. Considering the via density on the PCB, it is generally D1=D2+0.41mm.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(3) Signal traces on the PCB should not be changed layers as much as possible, that is, vias should be minimized;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(4) Using a thinner PCB helps reduce the two parasitic parameters of vias;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(5) Power and ground pins should be connected vias as close as possible, and the leads between the vias and the pins should be as short as possible, as they will increase inductance. At the same time, power and ground leads should be as thick as possible to reduce impedance;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">(6) Place some grounding vias near the vias for signal layer switching to provide short-distance loops for the signals. Of course, specific problems need to be analyzed on a case-by-case basis during the design process. Considering both cost and signal quality, designers always hope that vias are as small as possible in high-speed PCB design, so that more wiring space can be left on the board. In addition, the smaller the via, the smaller its parasitic capacitance, which is more suitable for high-speed circuits. In high-density PCB design, the use of non-through-hole vias and the reduction of via size have brought about an increase in cost. Moreover, the size of vias cannot be reduced indefinitely. It is limited by the drilling and electroplating processes of <a href=\"https:\/\/geyuanelectronics.com\/pcb\/pcb-manufacturing\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/pcb\/pcb-manufacturing\/\">PCB manufacturers<\/a>. A balance should be given in the via design of high-speed PCBs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Via selection in standard PCBs<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">In general PCB design, the parasitic capacitance and inductance of vias have a relatively small impact on the PCB design. For 1-4 layer PCB designs, 0.36mm\/0.61mm\/1.02mm vias (drill holes\/pads\/POWER isolation areas) are generally preferred. For some signal lines with special requirements (such as power lines, ground lines, clock lines, etc.), 0.41mm\/0.81mm\/1.32mm vias can be used, or other sizes of vias can be selected according to the actual situation.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Non-through-hole technology<\/strong> <strong>in PCB via design<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Non-through-hole vias include blind vias and buried vias. The application of blind and buried vias in non-through-hole via technology can significantly reduce the size and weight of PCBs, reduce the number of layers, improve electromagnetic compatibility, enhance the features of electronic products, reduce costs, and also make the design process simpler and faster.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In traditional PCB design and manufacturing, vias present numerous problems. Firstly, they occupy a significant amount of usable space. Secondly, a large number of vias clustered together create substantial obstacles for routing within multi-layer PCBs. These vias consume the space required for routing, and their dense penetration through the surfaces of power and ground layers can disrupt their impedance characteristics, potentially causing them to fail. Furthermore, conventional mechanical drilling is 20 times more labor-intensive than using non-through-via techniques.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">In PCB design, although the sizes of pads and vias have gradually decreased, if the board layer thickness does not decrease proportionally, the aspect ratio of through-holes will increase, which reduces reliability. With the maturity of advanced laser drilling and plasma dry etching technologies, the application of small, non-through-hole blind vias and small buried vias has become possible. If the diameter of these non-through-hole vias is 0.3mm, the resulting parasitic parameters are about 1\/10 of those of conventional vias, improving PCB reliability. Because of the use of non-through-hole technology, there are fewer large vias on the <a href=\"https:\/\/geyuanelectronics.com\/pcb\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/pcb\/\">PCB<\/a>, thus providing more space for traces.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">The remaining space can be used for large-area shielding to improve EMI\/RFI performance. Simultaneously, more remaining space can be used for partial shielding of components and critical nets in inner layers, ensuring optimal electrical performance. The use of non-through-vias facilitates easier fan-out of component leads, making it easier to route high-density pin devices (such as BGA-packaged devices), shortening interconnect lengths, and meeting the timing requirements of high-speed circuits.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>What is the difference between PCB vias and component holes?<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">In PCB design, there is a difference between vias and component holes, and they should never be used interchangeably.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Vias generally serve to facilitate conduction between two sides, and the conventional processing method is to apply an oil coating.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Component holes are typically designed as insertion holes for use during insertion soldering.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">If vias and component holes are used interchangeably, when selecting via cover ink, the through holes will be covered or blocked by ink, making it impossible to effectively control the size. Another situation is that component holes are mistakenly used as vias. In this case, when the software automatically closes the via window, it cannot effectively identify the via, resulting in vias that need cover ink not being covered.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Why choose Geyuan Electronics to manufacture your high-volume PCB products?<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Geyuan Electronics is an AI-driven, one-stop intelligent manufacturing infrastructure platform for electronic products. By integrating industrial software and engineer ecosystems, <a href=\"https:\/\/geyuanelectronics.com\/services\/oem-and-odm\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/services\/oem-and-odm\/\">original equipment manufacturer (OEM)<\/a> supply chain ecosystems, and flexible manufacturing ecosystems, we have built a closed-loop ecosystem for electronic product manufacturing and supply chain, committed to making hardware innovation simpler. Since 2024, we have been developing the &#8220;Geyuan Solution,&#8221; which boasts superior IoT solution design capabilities; AI Agents and electronic design automation tools; advanced internal manufacturability design analysis tools; a one-stop electronic component procurement service system; a high-reliability multilayer PCB R&amp;D and intelligent manufacturing system; SMT assembly; <a href=\"https:\/\/geyuanelectronics.com\/services\/printed-circuit-board-assembly\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/services\/printed-circuit-board-assembly\/\">PCBA<\/a>; and one-stop services for electronic product R&amp;D and contract manufacturing. We provide customers with a one-stop intelligent solution that connects design, production, procurement, and delivery, reshaping the fragmented and information-asymmetric model of traditional electronic product manufacturing, improving the efficiency of the entire chain from design to mass production, and creating value for users&#8217; creative ideas.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Summarize<\/strong><strong><\/strong><\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">This article not only summarizes PCB via design techniques compiled by the engineering team at Geyuan Electronics, but also covers fundamental information about vias and current advanced PCB via technologies. Following these rules and design techniques can significantly improve signal integrity, thermal management efficiency, and first-pass yield. It is essential to run DRC (Design Rule Check) in the later stages of the design process and optimize according to the PCB manufacturer&#8217;s process specifications. If you are currently looking for a professional PCB manufacturer to mass-produce your PCB products, please <a href=\"https:\/\/geyuanelectronics.com\/contact\/\" data-type=\"link\" data-id=\"https:\/\/geyuanelectronics.com\/contact\/\">contact us<\/a> for assistance.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Via Design Techniques in PCB Design In PCB design, via design is a crucial factor. It consists of the hole, the surrounding pad area, and the POWER layer isolation area, and is generally classified into three types: blind vias, buried vias, and through-hole vias. The engineering team at Geyuan Electronics, through analysis of parasitic capacitance [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"content-type":"","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[1,22,9,24,25],"tags":[],"class_list":["post-12747","post","type-post","status-publish","format-standard","hentry","category-all-blog","category-multilayer-pcb-blog","category-pcb-blog","category-pcb-design-blog","category-pcb-manufacturing-blog"],"_links":{"self":[{"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/posts\/12747","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/comments?post=12747"}],"version-history":[{"count":0,"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/posts\/12747\/revisions"}],"wp:attachment":[{"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/media?parent=12747"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/categories?post=12747"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/geyuanelectronics.com\/pt\/wp-json\/wp\/v2\/tags?post=12747"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}