Guide to Avoiding Custom PCB Via Design Errors

In multilayer PCB design, vias are critical structures connecting different circuit layers, and their design directly impacts circuit performance, production costs, and reliability. Furthermore, vias are key structures connecting conductive traces across different layers in multilayer PCBs, and their design quality directly affects the circuit’s electrical performance, mechanical strength, and manufacturability. What may seem like a simple “hole” actually involves multiple considerations, including process compatibility and signal integrity. Properly designing via parameters (such as solder rings and aperture) is fundamental to avoiding later production failures and circuit malfunctions.

According to statistics from Geyuan Electronics ‘ engineering team , drilling costs account for 30% to 40% of the manufacturing cost of multilayer PCBs. Therefore, balancing performance and cost in high-speed, high-density designs has become a significant challenge for engineers. This article, written by our engineering team , combines industry standards and practical experience to explain the core points of via design in custom multilayer PCB projects , helping you avoid common pitfalls.

Basic Functions and Essence of Vias on Custom Multilayer Printed Circuit Boards

In printed circuit board (PCB) design, the core function of vias is to achieve electrical connections between different conductive layers of a multi-layer PCB, while also providing some mechanical fixing (such as assisting in the fixing of heavy components). Structurally, a via consists of three parts: a drill hole, a plated barrier, and an annular ring. Essentially a “vertical transmission line,” vias introduce parasitic inductance (typically 0.5-2nH) and parasitic capacitance (0.1-0.5pF) in high-frequency signal transmission, and these parameters increase with the via size. Therefore, via design must strike a balance between “connection reliability,” “signal integrity,” and “process feasibility,” ensuring drilling and plating quality while minimizing the impact on high-speed signals.

The Importance of Via Design in Multilayer PCBs

1. If the circuit is very simple, vias may not be needed, but vias are determined to be needed when designing a multi-layer PCB.

2. In the case of multilayer boards, vias can increase the density of components.

3. As the number of multilayer PCBs increases, the density of traces will become higher and higher. Vias can connect different traces on different layers of the PCB to each other, and vias act as vertical connection components.

4. Without vias, it is easy to get stuck in the routing process, and components from BGA, connectors, and even multi-layer PCBs will be densely packed.

5. Vias facilitate the transmission of signals and power between layers. Without vias, all components are on one plane, and there are surface mount components. However, surface mount components in multilayer PCBs cannot be routed on a single plane.

Geyuan Electronics’ engineering team’s experience in multilayer PCB via design

Via design is a crucial aspect of multilayer PCB engineering, where a single change can have far-reaching consequences. By appropriately selecting dimensions, standardizing spacing, and optimizing fan-hole strategies, it’s possible to meet high-speed signal requirements while controlling costs. More importantly, close communication with the PCB manufacturer ‘s engineering team regarding process details is essential to translating design specifications into reliable products and standing out in a highly competitive market. Below are some experience summaries on PCB via design from Geyuan Electronics’ engineering team, accumulated from designing over 10,000 multilayer PCB projects for clients, for your reference.

Via size is not necessarily better the smaller it is; it must be balanced with process limitations

Vias consist of drill holes and surrounding pads. The size selection should follow these principles:

Inner and outer diameter specifications	The inner diameter of the through hole is ≥0.2mm (8mil), and the outer diameter is ≥0.4mm (16mil); in extreme cases, the outer diameter can be reduced to 0.35mm (14mil).
Empirical formula	The outer diameter is typically twice the inner diameter ± 2 mil. For example, an 8 mil inner diameter corresponds to an 14/16/18 mil outer diameter.
Process limitations	Too small a hole diameter increases the risk of drilling deviation, and when the hole depth exceeds 6 times the hole diameter, it is difficult to guarantee the uniformity of electroplating.
Design suggestions	For high-speed circuits, smaller vias are preferred to reduce parasitic capacitance, but the process capabilities must be confirmed with the PCB manufacturer to avoid blindly pursuing extreme dimensions. Too small a via diameter increases the risk of drilling misalignment, and when the via depth exceeds six times the via diameter, plating uniformity is difficult to guarantee.

High-level design must be used cautiously when burying blind holes to control costs

For BGA packages (pin pitch ≥ 0.65mm), buried blind vias are not recommended due to their high cost. If they must be used, first-order blind vias (such as TOP-L2 or BOTTOM-L2) are recommended, with an inner diameter of 0.1mm (4mil) and an outer diameter of 0.25mm (10mil). While higher-order blind vias can increase wiring density, the manufacturing difficulty and cost increase exponentially.

Vias and pads should avoid the risk of tombstoning

While placing vias directly on the pads can reduce lead inductance, it can cause solder paste to flow into the vias, leading to solder tombstoning .

Safety distance	It is recommended to maintain a 4-8 mil gap between vias and pad edges.
BGA area	The via should be centered between the two pads to avoid misalignment that could cause solder bridging and short circuits. After completion, the vias must be plugged and coated with solder paste to ensure the BGA solder balls are flat.

The via spacing design should prevent via breakage and ensure reliability

Too close a spacing between vias can easily cause drilling failure. Specifications require:

Minimum spacing	≥0.5mm (recommended), 0.35~0.4mm should be avoided at all costs, and ≤0.3mm is prohibited .
High-density areas	By using staggered arrangements or adjusting the aperture, space utilization can be optimized.

Orifice plugging oil is key to improving welding yield

For small-diameter through-holes (≤0.5mm) and special scenarios, plugging and sealing with oil is necessary:

Metal housing devices	The vias at the bottom of the main body need to be plugged to prevent short circuits with the outer casing.
Except for heat dissipation holes	Openings can be retained to enhance heat dissipation .

Fixed pads can be cleverly enhanced by using vias to improve reliability

The pads for headphone terminals, buttons, FPCs, etc., are susceptible to mechanical stress. During the design process, one to two vias can be added evenly to increase the adhesion of the copper foil and prevent the pads from falling off.

Fan-hole design requires a win-win strategy that balances signal integrity and cost

conventional chip device fan holes	It is recommended to place vias on the outside of the device, allowing inner layer traces to pass between the two vias, thus avoiding cutting the reference plane. Incorrect practices will increase routing complexity and compromise the integrity of the plane.
BGA fan holes	Vias must be strictly centered on the pads; they must not be offset or placed directly on the pads. Vias in the pads are prone to causing cold solder joints and may cut the power/ground plane, leading to signal integrity issues.

Considerations for via design in multilayer PCBs and standards for selecting solder rings and hole diameters

Solder rings and via diameters are core parameters in via design and need to be determined based on PCB thickness, copper foil thickness, and manufacturing process. We recommend standard selections for solder rings and via diameters (e.g., 0.7mm + 0.3mm). However, please note the following design considerations.

Drill Diameter

The borehole diameter, also known as the borehole diameter, determines the conductivity and parasitic parameters of the borehole.

Standard Selection	For standard PCBs (1.6mm thick), the recommended minimum hole diameter is 0.3mm (the limit for mechanical drilling is typically 0.2mm, while laser drilling can achieve as small as 0.1mm), with commonly used hole diameters ranging from 0.4mm to 0.6mm. For example, signal vias can be 0.4mm, while power vias (for high current carrying capacity) can be 0.6mm to 1.0mm.
Matching plate thickness	The aspect ratio of aperture to board thickness should be ≤1:10 (e.g., for a board thickness of 1.6mm, the maximum aperture is 0.16mm). Exceeding this ratio will result in uneven plating on the hole walls (thickness difference >20%), affecting conductivity reliability. If the board thickness reaches 2.0mm, the aperture is recommended to be ≥0.3mm.

Annular Ring

A solder ring is a ring of copper foil surrounding a via, used to enhance the connection between the via and the copper foil of the same layer. Its width (solder ring width = (pad diameter – via diameter) / 2) must meet the following requirements:

Minimum weld ring width	The standard process requires a pad diameter of ≥0.15mm (i.e., pad diameter = hole diameter + 0.3mm). For example, when the hole diameter is 0.4mm, the pad diameter should be ≥0.7mm (0.7-0.4=0.3mm, and the single-sided solder ring is 0.15mm).
High-speed signal optimization	For high-frequency signals (≥1GHz), the via ring can be reduced to 0.1mm (but process capabilities need to be confirmed with the manufacturer) to reduce parasitic capacitance.
Power Via Reinforcement	The width of the solder ring for high-current vias can be increased to over 0.2mm, enhancing the connection strength with the copper foil and preventing overheating caused by concentrated current.

Typical combination example of multilayer PCB via design at Geyuan Electronics

Signal via	With a 0.4mm aperture and a 0.7mm pad diameter (0.15mm solder ring), it is suitable for most digital signals and low-frequency analog signals.
Power Via	Aperture 0.6mm + pad diameter 1.0mm (solder ring 0.2mm) to meet 1A-3A current transmission (when copper thickness 1oz=35μm).
High-density areas	With a hole diameter of 0.3mm and a pad diameter of 0.6mm (0.15mm solder ring), it is suitable for space-constrained areas such as the bottom of a BGA.

In multilayer PCB via design, special hole types require attention to the aspect ratio of the slots and the issue of hole bursts

Besides circular vias, slot holes are required in special scenarios, and their design requires extra attention:

Slot Hole

The slots are rectangular or oval, used for connecting irregularly shaped pins (such as DIP pins of connectors) or for high-current transmission.

Aspect Ratio Limitation	The ratio of the length to the width of the slot should be ≤5:1 (e.g., when the width is 0.5mm, the maximum length is 2.5mm). Exceeding this ratio can easily cause the tool to deviate during drilling and result in a rough hole wall.
Coating requirements	The corners of the slots must be rounded (radius ≥ 0.2 mm) to avoid stress concentration in the plating at right angles, which could lead to cracking; the plating thickness on the hole wall must be ≥ 20 μm to ensure reliability under high current.

Blowhole prevention

Pitting refers to the separation of the plating on the hole wall from the weld ring during welding or high-temperature environments. Cause analysis and solutions:

reason	measure
Insufficient weld ring width (<0.1mm) leads to thermal stress and peeling at high temperatures;	The weld ring width is ≥0.15mm to ensure mechanical connection strength;
Pinholes or bubbles in the plating on the hole wall can cause flux to seep in and cause expansion during welding.	Manufacturers are required to use an “acidic copper plating” process (which is more uniform than alkaline copper plating) and conduct a coating adhesion test (peel strength ≥ 0.5 N/mm).

Design recommendations for impedance effects and via density in multilayer PCB design

Via design needs to balance signal integrity and layout rationality:

Impedance Influence and Optimization

High-frequency signal via	Each additional via will reduce the differential pair impedance by 2-5Ω (e.g., a 100Ω differential pair may drop to 95Ω), requiring compensation during routing by fine-tuning the trace width (e.g., increasing the trace width by 0.02mm).
Reduce the number of vias	High-speed signals (such as PCIe 4.0) should avoid crossing layers. If crossing layers is necessary, the number of vias should be ≤2, and the distance between the two vias should be ≥5mm (to reduce mutual coupling).
Grounding via surround	Place 2-4 grounding vias around the high-speed signal via (at a distance of ≥3 times the via diameter) to form a “shielding ring” and reduce radiation and crosstalk.

Arrangement density control

Via spacing	The center-to-center distance between adjacent vias should be ≥ 2 times the hole diameter (e.g., for a 0.4mm via, the spacing should be ≥ 0.8mm) to avoid hole displacement or hole wall connection (short circuit risk) caused by vibration during drilling.
BGA area vias	The vias below the BGA solder joints should be staggered from the solder joint positions and at least 0.3mm away from the edge of the solder joint to prevent solder from flowing into the vias during soldering (leading to cold solder joints).

Other precautions

Lead-free soldering compatible	The through-hole plating must contain lead (or lead-free alloy such as Sn-Ag-Cu) and have a thickness of ≥2μm to ensure that it does not oxidize or peel off during reflow soldering at 260℃.
Solder mask	Non-soldering vias (such as signal vias) must be covered with a solder mask to prevent solder bridging; if testing is required, partial solder mask opening can be performed.

Validation recommendations for multilayer PCB via process design

The reliability of via design needs to be ensured through process verification:

DFM Inspection	Use the DFM tool in PCB design software (such as Altium’s “Manufacturing Check”) to verify that the via parameters meet the manufacturer’s process capabilities (e.g., hole diameter ≥ 0.3mm, solder ring ≥ 0.15mm).
Sample testing	The first PCB design needs to undergo via reliability testing.
Continuity test	The resistance across the via should be less than 0.1Ω when measured with a multimeter.
Thermal shock test	After 100 cycles from -40℃ to 125℃, the via resistance change rate is ≤10%;
Tensile test	A 5N pulling force was applied to the power via for 10 seconds, and there was no detachment or breakage.
Communicate with the manufacturer	Before submitting the design, provide the PCB manufacturer with a via parameter table (hole diameter, solder ring, quantity) to confirm its process feasibility (especially for special requirements such as laser drilling and thick plate vias).

Why choose Geyuan Electronics as your custom multilayer PCB manufacturing partner?

Geyuan Electronics is an AI-driven one-stop intelligent infrastructure platform for the electronics industry. By integrating industrial software and engineer ecosystems, original equipment manufacturer (OEM) supply chain ecosystems, and flexible manufacturing ecosystems, we have built a closed-loop ecosystem in the electronics supply chain field, committed to making hardware innovation simpler. Since our inception, we have developed a range of businesses including the “Geyuan Solution” with superior IoT solution design capabilities, AI Agents and electronic design automation tools, manufacturability design analysis tools, one-stop electronic component procurement services, a high-reliability multilayer PCB R&D and manufacturing intelligent platform, and a one-stop SMT assembly and PCBA outsourcing service platform. We provide customers with one-stop intelligent solutions that connect design, production, procurement, and delivery, reshaping the traditional fragmented and information-asymmetric model of the electronics industry, improving the efficiency of the entire chain from design to mass production, and creating value for users’ creative ideas.

Summarize

Via design is the “invisible pillar” of PCB reliability. Its parameter selection must follow the principle of “process-based, performance-oriented”: For standard scenarios, the classic combination of 0.4mm via diameter + 0.7mm pad is used; for high-frequency scenarios, the number of vias is reduced and the solder ring is optimized; for high-current scenarios, the via diameter and solder ring width are increased. It’s crucial to remember during design: vias are not “the smaller the better” or “the more the better.” Instead, they must meet connectivity requirements while minimizing manufacturing risks through DFM checks and process verification. A well-designed via system can effectively avoid problems such as “via bursts” and “cold solder joints” during mass production, ensuring long-term stable circuit operation. If you have custom multilayer PCB projects and need to find partner suppliers for design and mass production, please contact us for assistance.