A comprehensive guide to PCB stacked via design strategies and collaborative optimization methods for process compatibility

If you’re looking for a collaborative approach to optimizing PCB design and process compatibility using stacked vias, you’ve come to the right place. Stacked vias are key components in High-Density Interconnect (HDI) boards, enabling efficient layer transitions in compact designs. But how do you ensure they’re implemented correctly? And how else can this process be collaboratively optimized? This guide delves into stacked via design rules, real-world design challenges and solutions, and stacking vias according to IPC standards to help you master their use.

What are stacked vias?

Stacked vias are vertical interconnects placed directly on top of each other to connect multiple layers in a printed circuit board (PCB). Unlike offset interleaved vias, stacked vias save space, making them ideal for space-constrained HDI designs. The importance of stacked vias lies in their ability to support high-speed signals and dense layouts. However, improper design can lead to problems such as signal attenuation, manufacturing defects, or structural flaws. This is why understanding the rules and best practices of stacked via design is crucial for any PCB engineer seeking reliable, efficient boards. In current market applications, PCBs with this design are typically used in complex electronic products such as smartphones, tablets, and advanced medical devices.

Why is PCB stack-up necessary?

Developing PCB stack-ups is crucial for designing high-efficiency circuit boards . Such stack-up designs offer numerous advantages. Firstly, they enable multi-layered PCB structures, which improve energy distribution, prevent electromagnetic interference (EMI), limit crosstalk, and support high-speed signal transmission. Therefore, the primary purpose of this stack-up design is to place multiple electronic circuits on a single board through multiple layers. Beyond this, the PCB stack-up structure provides other significant advantages. These include minimizing the board’s vulnerability to external noise and reducing crosstalk and impedance issues in high-speed systems. A good PCB stack-up can also help ensure lower final production costs. By maximizing efficiency and improving electromagnetic compatibility throughout the project, PCB stack-ups can effectively save time and money.

Guidelines on PCB stacking via design strategies and process compatibility optimization methods in real-world projects.

The following is a summary of PCB stacked via design strategies and related process compatibility optimization methods, compiled by the engineering team at Geyuan Electronics based on years of practical projects. PCB stacked via design is not simply about “aligning multiple layers of vias”; it requires consideration of three key dimensions: electrical performance (signal integrity, impedance matching), mechanical reliability (load capacity, stress resistance), and process compatibility (drilling accuracy, plating feasibility) . An impedance matching deviation of 5Ω can cause high-frequency signal reflectivity to deteriorate from -20dB to -15dB; an alignment accuracy exceeding ±0.01mm can increase plating breakage rate from 1% to 8%; and process incompatibility can lead to batch scrap (yield <70%). Today, we not only analyze the core design principles of PCB stacked vias but also combine specific parameters and case studies encountered by our team in actual projects to help you achieve “high-performance, high-reliability, and mass-producible” stacked via designs.

Prioritize electrical performance and ensure signal integrity and impedance matching.

As a “channel” for interlayer signal transmission, the electrical performance of stacked vias directly determines the overall signal quality of the PCB, and impedance, parasitic parameters and signal crosstalk need to be carefully controlled.

1. Impedance matching design (core principle)

Impedance target: The impedance of the stacked vias must be consistent with the impedance of the connected lines (e.g., a 50Ω RF line corresponds to a 50Ω stacked via) to avoid signal reflection caused by impedance abrupt changes;

Impedance calculation method:

Formula: Z = (60 / √εr) × ln (4h/d) (Simplified formula, εr is the dielectric constant of the PCB substrate, h is the substrate thickness, and d is the via diameter);

Example: For FR-4 substrate (εr=4.4), h=0.2mm, d=0.2mm, the calculated Z≈52Ω, which is close to the target of 50Ω. Z=50Ω can be achieved by fine-tuning the aperture (e.g., d=0.21mm).

Optimization strategy:

Adjusting the aperture	As the aperture increases, the impedance decreases (e.g., as d increases from 0.18mm to 0.22mm, Z decreases from 55Ω to 48Ω).
Change substrate	In high-frequency applications, use substrates with low dielectric constants (such as Rogers RO4350B, εr=3.48) to reduce impedance deviation.
Add grounding via	A grounding via (0.5mm spacing) is placed within 1mm around the stacked vias to form a “shielding ring” and stabilize the impedance (deviation ≤ ±2Ω).
Case	Our team initially designed the via impedance of a 5G RF PCB stack with an impedance of 58Ω (target 50Ω) and a signal reflectivity of -14dB (exceeding the standard). By increasing the via diameter from 0.18mm to 0.22mm and adding two grounding vias around it, the impedance dropped to 50.5Ω and the reflectivity was optimized to -22dB, meeting the requirements.

2. Parasitic parameter control (reducing signal loss)

Parasitic inductance and capacitance

Parasitic inductance (L)	The L value of stacked vias mainly comes from the via wall length. The shorter the length, the smaller L is (e.g., L=2nH for a 0.3mm via depth, L=4nH for a 0.6mm via depth). The loss of high-frequency signals (>10GHz) increases with the increase of L.
Parasitic capacitance (C)	C mainly comes from the coupling between the hole wall and the grounding layer. The larger the hole diameter and the closer the grounding layer is, the larger C will be (e.g., C=0.8pF for d=0.2mm and grounding layer distance of 0.1mm). Excessive C will cause the signal rise time to slow down (e.g., a 100ps rise time signal becomes 150ps due to C=1pF).

Optimization strategy

shorten hole depth	Prioritize blind/buried via stacking (hole depth 0.2-0.5mm) and avoid through-hole stacking (hole depth 1.6mm, L=8nH);
Increase grounding distance	The distance between the ground plane and the via increased from 0.1 mm to 0.2 mm, and C decreased from 0.8 pF to 0.4 pF;
Differential stacked vias	High-frequency differential signals (such as USB 4.0) use a pair of stacked vias with differential impedance matching (such as 100Ω) to reduce the influence of parasitic parameters.

3. Signal crosstalk suppression (multiple via scenarios)

Sources of crosstalk: Electromagnetic coupling between adjacent stacked vias. The smaller the spacing and the higher the signal frequency, the more severe the crosstalk (e.g., a 25GHz signal with a spacing of 0.5mm has a crosstalk of -18dB).

Suppression strategy

Increase spacing	When the spacing between stacked vias is ≥2 times the via diameter (e.g., a spacing ≥0.4mm corresponds to a 0.2mm via diameter), crosstalk of 25GHz signals can be reduced to below -25dB;
Grounding isolation	By placing grounding vias (0.3mm spacing) between adjacent stacked vias to form an “isolation wall”, crosstalk is further reduced by 5-8dB;
Layered layout	Distribute stacked vias for high-frequency signals (such as radio frequency) and low-frequency signals (such as power) on different layers to reduce cross-layer crosstalk.

Achieve mechanical reliability design to ensure long-term stable operation

Stacked vias need to withstand the stress during PCB manufacturing (lamination, drilling) and use (temperature cycling, vibration). Insufficient mechanical reliability can lead to “plating cracking and pad detachment”, so it is important to control the structural strength and stress resistance.

1. Structural strength design

Pad reinforcement:

Increase pad size	The pad diameter increased from 0.3mm to 0.4mm, the connection area between the pad and the circuit increased by 44%, and the tensile strength increased from 5N to 8N;
Add teardrop-shaped transition	Teardrop design (0.1mm radius) at the connection between the pad and the circuit is used to avoid stress concentration (stress is reduced from 100MPa to 60MPa).

Hole wall thickness control:

Hole coating thickness	The coating thickness is ≥25μm (IPC standard). The thicker coating (35μm) has 50% higher bending resistance than the thinner coating (20μm). In the PCB bending test (bending radius 5mm), the breakage rate is reduced from 10% to 2%.
Avoid uneven hole wall thickness	The thickness deviation of the coating on each hole wall is ≤±3μm. Unevenness will lead to local stress concentration and increase the cracking rate after high temperature cycling (-40~125℃).

2. Stress-resistant design (adapting to environmental changes)

Temperature cycling adaptability:

Choose materials with matching coefficient of thermal expansion (CTE).	The difference between the substrate CTE and the coating CTE around the stacked vias is ≤5ppm/℃ (e.g., FR-4 substrate CTE is 13ppm/℃, copper coating is 17ppm/℃, difference is 4ppm/℃), reducing coating fatigue caused by temperature cycling;
Resin filling the pores	For high-reliability applications (automotive electronics, medical devices), epoxy resin (CTE 8ppm/℃) is filled into the stacked vias to enhance resistance to temperature stress. After 1000 temperature cycles, the cracking rate decreases from 8% to 0.5%.

Vibration adaptability:

Add support structure	Reinforcing ribs (0.2mm wide) were designed in the area where the stacked vias were located to improve the local stiffness of the PCB. After vibration testing (10-2000Hz, 30g), the via detachment rate decreased from 5% to 0.3%.
Avoid edge layout	Stacked vias should be at least 2mm from the PCB edge. Vibration stress in the edge area is 2-3 times that in the center area, which can easily lead to via damage.

Achieving process compatibility design ensures mass production capability and low cost.

Stacked via designs must be compatible with existing PCB manufacturing processes (drilling, electroplating, lamination) to avoid soaring costs or declining yield rates due to process limitations.

1. Drilling accuracy compatible

Alignment accuracy requirements:

Multi-layer via center deviation	Multi-layer through-hole center deviation ≤ ±0.01mm (high-precision drilling machine, such as Hitachi SE-8000, positioning accuracy ±0.005mm);
Avoid ultra-small aperture	Hole diameter ≥ 0.08mm (conventional drilling machines can drill as small as 0.07mm, but the pass rate is < 80%), hole diameter ≥ 0.1mm, pass rate ≥ 95%;

Drilling sequence optimization:

order	First drill the intermediate layer buried holes, then drill the surface layer blind holes, and finally laminate (to avoid alignment deviations caused by drilling after lamination).
Example	For 8-layer PCB stacked vias, first drill buried vias L3→L4 and L5→L6, and then drill blind vias L1→L2 and L7→L8 after lamination, with an alignment deviation of ≤±0.008mm.

2. Electroplating process compatible

Coating uniformity assurance:

Aperture and depth	The ratio of aperture to depth should be ≤1:3 (e.g., a 0.2mm aperture corresponds to a depth ≤0.6mm). A ratio that is too large (1:5) will result in uneven current distribution within the aperture and a coating thickness deviation >±5μm.
Pulse electroplating	Compared to DC electroplating, pulse electroplating (frequency 1000Hz) can reduce the thickness deviation of the plating layer inside the hole from ±6μm to ±2μm;

Pre-treatment cleaning:

When designing, avoid creating “dead corners” inside the holes (such as right-angle transitions in stepped holes). Dead corners are prone to retaining contaminants, resulting in a plating void rate exceeding 10%. Rounded corner transitions (radius 0.05mm) are required.

3. Compatible with lamination process

Lamination parameter matching:

substrate thickness in the stacked via area	The substrate thickness deviation in the stacked via area should be ≤±5% (e.g., if the design layer thickness is 0.2mm, the actual thickness is 0.19-0.21mm). Excessive deviation will cause via misalignment after lamination.
Lamination temperature	The lamination temperature gradient should be ≤2℃/min (heating rate) to avoid sudden temperature rise that could cause substrate deformation and affect via alignment.

Solder mask compatibility:

Opening of solder resist layer

The solder mask opening size should be 0.05-0.1mm larger than the pad (e.g., a 0.4mm pad corresponds to a 0.45-0.5mm opening) to avoid the solder mask covering the pad, which could lead to poor soldering.

summary

PCB stacked via design requires “multi-dimensional collaboration”: electrical performance ensures signal quality, mechanical reliability guarantees long-term stability, and process compatibility enables mass production. All three are indispensable, and design parameters need to be dynamically optimized according to specific scenarios (high frequency, high reliability, high density).

Common challenges of stacking vias and how to avoid them

While stacked vias offer significant advantages, they also present challenges that, if left unaddressed, can impact your design. Here are some common issues and solutions:

Misalignment of drilling	Misaligned drill bits can result in disconnected connections or weak stacked vias. Use advanced design tools with automatic alignment checks and partner with manufacturers who achieve precision using laser drilling.
thermal stress	Through-holes spanning multiple layers are prone to thermal expansion stress, which can lead to cracking. Limit the through-hole height and use materials with a matching coefficient of thermal expansion (CTE) for both the through-holes and the circuit board substrate.
Signal loss	High-speed signals transmitted via stacked vias may experience signal loss due to impedance discontinuities. Minimize via length and use backdrilling to remove unused via stubs to reduce signal reflection.

PCB Stack-up Design Considerations

The following is a more detailed discussion of the design considerations for each PCB stack-up:

number of floors	The appropriate number of layers should be determined based on the complexity of the circuit and the required functionality. Factors such as signal density, power distribution, and noise isolation should be considered.
Signal Integrity	Planning the arrangement of signal layers is crucial to minimizing signal attenuation and maintaining good signal integrity. Proper layer ordering, impedance control, and controlled dielectric constants are essential for managing signal integrity issues such as crosstalk, signal reflection, and impedance mismatch.
Power and ground plane	Dedicated power supplies and ground planes are allocated to provide a stable, low-impedance power distribution network. Ground planes help reduce noise, improve signal quality, and promote heat dissipation.
Planar decoupling	Including decoupling capacitors near the power and ground planes helps suppress high-frequency noise and provide clean power to sensitive components. Proper placement and selection of decoupling capacitors are crucial for effective decoupling.
Heat precautions	Incorporate thermal vias and distribute thermal planes within the stack to manage heat dissipation. Consider the heat generated by the components and design the stack to ensure adequate thermal management.
EMI/EMC Precautions	Plan the layer stack-up to minimize electromagnetic interference (EMI) and ensure electromagnetic compatibility (EMC). This involves carefully placing signal and power layers, using shielding layers where necessary, and considering appropriate grounding techniques.
Manufacturing restrictions	When designing the stack-up, consider the PCB manufacturer’s manufacturing capabilities and limitations, such as minimum trace width and spacing, minimum drill hole size, and material availability.
Material selection	Choose the appropriate laminate material based on the required electrical performance, thermal performance, and cost considerations. Different materials have different dielectric constants, loss tangents, and thermal conductivity, all of which affect the overall performance of the PCB.
Signal layer sorting	Determining the order of signal layers in a stack is crucial for minimizing crosstalk and ensuring efficient routing. Grouping high-speed signal layers and separating them from low-speed layers can help manage signal integrity.
Controlled impedance	Designing stack-ups with controlled impedance for critical high-speed signals involves calculating and controlling trace widths, dielectric thicknesses, and interlayer spacing to achieve the desired impedance values.

Compliant with Stacked Via IPC standards

Stacked IPC standards provide guidelines for ensuring the quality and reliability of PCB manufacturing. These standards, developed by the Printed Circuit Association, cover all aspects of via design, including dimensions, spacing, and manufacturing processes. Key IPC standards related to stacked vias include:

IPC-2221	This standard outlines general design principles for PCBs, including via spacing and gaps. It recommends minimum gaps based on voltage levels to prevent electrical breakdown. For example, at 100V, a gap of at least 0.25 mm between conductive components is recommended.
IPC-6012	It focuses on the qualifications and performance of rigid PCBs. It specifies the requirements for via plating thickness and quality to ensure that stacked vias can withstand thermal and mechanical stresses. For reliability, a minimum plating thickness of 20-25 micrometers is typically required.
IPC-4761	Covering should be done through protection and filling methods. For stacked vias, conductive filler or capping is recommended to prevent voids and enhance structural integrity.

Adhering to these standards not only improves design reliability but also ensures compatibility with most manufacturers. Non-compliance can lead to manufacturing delays or circuit board failures during testing or operation.

Collaborating with Geyuan Electronics on a custom PCB project featuring stacked vias

a custom PCB project with stacked vias requires close collaboration with your PCB manufacturer. When you’re considering this type of project with Geyuan Electronics, here are some tips to ensure a smooth process:

Share your detailed design files	Provide us with clear and accurate design documents, including via specifications, stack-up details, and material requirements.
Discuss capabilities and arrangements as early as possible	Not all manufacturers have the equipment or expertise to handle complex stacked via designs , but Geyuan Electronics’ engineering team can discuss these with you in advance . Therefore , please confirm the features with us before finalizing your design , such as minimum via size and stacking constraints.
Request Design for Manufacturability (DFM) Feedback	Many manufacturers offer Design for Manufacturing (DFM) reviews to identify potential design problems, such as alignment or aspect ratio issues, before production begins. Geyuan Electronics is no exception.
Test plan	We have partnered with Geyuan Electronics to establish testing protocols, such as X-ray inspection for void detection, to ensure the reliability of stacked vias.

Summarize

Stacked vias are a game-changer in the high-density PCB industry, enabling smaller, faster, and more powerful electronic devices. This article provides a fresh perspective on the fundamentals of stacked via design for PCBs, summarizing our design strategies in practical applications, collaborative optimization methods for process compatibility, and key issues to avoid. By following the best practices outlined in this comprehensive guide to stacked vias, you can optimize custom PCB layouts for improved performance and manufacturability. If your project requires a professional PCB manufacturer, please contact us. We handle everything from design optimization and prototyping to high-volume assembly and production.