How should the size, location, and solder mask of vias within PCB pads be controlled?

In PCB design, vias (through-holes), blind vias (semi-through-holes), and buried vias (inner layer vias) are core structures for achieving interlayer electrical connections. Their design rationality directly affects the PCB’s signal integrity, mechanical strength, and manufacturing feasibility. Specifications need to be established from three aspects: size matching, layout rules, and impedance control. Parameters should be optimized based on the application scenario to avoid problems such as signal crosstalk and via wall breakage. This article, compiled by the PCB engineering team at Geyuan Electronics, discusses how to control the size, location, and solder mask of vias within PCB pads. You can learn more about the relevant design ideas and basic principles.

Relationship between pads and vias in PCB

A pad is a basic design object. Pads are used to attach components to a circuit board and establish connection points between component leads and on-board traces. Pads can exist on a single layer, such as surface mount device pads; or they can be three-dimensional through-hole pads, having a cylindrical body in the Z-plane (vertical direction) and flat areas on each (horizontal) copper layer. The cylindrical body of the pad is formed during the pcb manufacturing process when drilling holes and plating the hole walls on the circuit board. In the X and Y planes, pads can be circular, rectangular, octagonal, rounded rectangles, chamfered rectangles, or custom shapes. Pads can be used independently as freeform pads in a design, but more commonly they are used in a PCB library editor along with other basic objects to form component packages.

A via is a fundamental design object. Vias are used to establish vertical electrical connections between two or more electrical layers on a PCB. A via is a three-dimensional object with a cylindrical body in the Z-plane (vertical direction) and a flat, annular region on each (horizontal) copper layer. The cylindrical body of a via is formed during the manufacturing process when drilling and plating the hole walls. Vias are circular in the X and Y planes, similar to circular pads. The main difference between vias and pads is that vias can span all layers of a PCB (from top to bottom), and can also bridge from a surface layer to an inner layer, or between two inner layers.

Why is via design in PCB pads important?

If you’re working with BGA or fine-pitch packages, you’ve heard of through-hole PCBs. Instead of placing vias next to the pads, engineers place them directly inside the pads. Why? Because this saves space and reduces inductance in high-speed designs. But there’s a problem: these vias must be filled and plated; otherwise, solder will flow into the vias during assembly, causing poor connections. This is why through-hole PCB designs always employ fill-in PCB technology.

Definition of pads in PCB

The outer shape of through-hole pads is typically circular, square, or oval. Specific dimensional definitions are detailed below.

Aperture size	If the actual pin is round: the hole diameter = actual pin diameter + 0.20~0.30mm (approximately 8.0~12.0MIL); If the actual pin is square or rectangular: the hole diameter = the actual pin diagonal size + 0.10-0.20mm (approximately 4.0-8.0MIL).
Pad size	The standard pad size is approximately equal to the hole diameter plus 0.50 mm (20.0 MIL).

PCB pad design specifications

In PCB design, pads should also be designed according to the IPC-7351 standard. IPC-7351 specifies pad design guidelines for component types, sizes, and packaging, which ensures the use of more components and helps reduce material usage. Although some electronic components do not conform to this standard, IPC-7351 can help with precise positioning and reduce variation.

Therefore, the minimum diameter of each pad should not be less than 0.25mm, and the maximum diameter of the entire pad should not exceed three times the component hole diameter. Generally, through-hole components use round pads with a pad diameter at least 1.8 times the hole diameter; the pad diameter for single-sided boards should not be less than 2mm; the optimal ratio of pad size to through-hole diameter for double-sided boards is 2.5. For components suitable for automatic insertion machines, the pad size for double-sided boards should be their standard hole diameter + 0.5 to + 0.6mm .

The distance between the edges of two pads should be greater than 0.4mm, and the distance between the edges of two pads in a row perpendicular to the direction of the wave crest should be greater than 0.5mm (at this time, this row of pads can be regarded as a wire group or socket, and the distance between them is too close, which can easily lead to bridging) .

For dense wiring, oval and oblong connector pads are recommended. The diameter or minimum width of single-sided PCB pads should be 1.6mm, or ensure a 0.3mm single-sided PCB with a 0.2mm solder ring on one side; excessively large pads can easily cause unnecessary bridging. For highly dense wiring, circular and oblong pads are recommended. The diameter of these pads is typically 1.4mm, or even smaller.

Pads with apertures exceeding 1.2mm or pad diameters exceeding 3.0mm should be designed as star or clover pads. For through-hole components, to avoid copper foil breakage during soldering, the joints of single-sided boards should be completely covered with copper foil; while double-sided boards should at least have teardrop-shaped pads .

For all connectors and other load-bearing or heavy components, the copper foil covering the lead wires within 2mm should be maximized, and there should be no empty pads to ensure sufficient solder absorption. This prevents the copper foil from easily peeling off when the socket is subjected to external force. For large components (such as transformers, electrolytic capacitors with a diameter of 15.0mm or more, high-current sockets, etc.), increase the copper foil and solder coverage area as shown in the figure below; the shaded area should be at least equal to the pad area. Alternatively, design them as quincunx or star-shaped pads.

All machine-insulated components must be designed with drip pads along the bend direction to ensure full solder joints at the bend. For horizontal components, the left and right legs should be bent inwards, and for vertical components, the left leg should be bent outwards with the right leg tilted downwards at 15° and the right leg tilted upwards at 15°. Ensure that the edge spacing between the component and the surrounding pads is at least 0.4 .

If there are large ground and power lines on the printed circuit board (area exceeding 500mm2), windows should be opened locally or the area should be designed as a grid fill.

Basic Design Guidelines for Via Dimensions, Locations, and Solder Mask in PCB Pads

The design of vias within PCB pads directly determines soldering reliability and signal integrity. Oversized vias can lead to insufficient copper foil on the pads (making it difficult to fix pins during soldering), and a positional offset exceeding 0.05mm can cause the via edge to extend beyond the pad (leading to solder loss). Unlike the pitfall of “designing based on experience,” scientific design must adhere to four key specifications: size matching, precise positioning, solder mask compatibility, and sufficient copper foil. Each specification has clear parameter standards and quantitative requirements to avoid design flaws that lead to subsequent manufacturing problems. Today, we analyze the core design specifications for vias within pads, combining specific parameters and case studies to help you master the key design points from size to solder mask.

Reference for Dimensional Control in Via and Pad Design

The size ratio of vias to pads is the core of the design. It is necessary to ensure that “the vias do not exceed the pad boundaries, and there is enough remaining copper foil on the pads for soldering”. The core parameters and standards are as follows:

1. Control the ratio of via diameter (Dv) to pad size (Dp)

Circular pads	The via diameter Dv ≤ 1/2 of the pad diameter Dp, and the remaining copper foil width at the pad edge ≥ 0.1mm (minimum soldering area requirement).
Example	The component’s circular pad Dp = 0.3mm, and the maximum Dv is 0.15mm (0.3 × 1/2). The remaining copper foil width = (0.3 – 0.15) / 2 = 0.075mm (close to 0.1mm, so choose carefully; it is recommended that Dv = 0.12mm, with a remaining width of 0.09mm).The component’s circular pad Dp = 0.4mm, Dv is at most 0.2mm, and the remaining copper foil width = (0.4-0.2)/2 = 0.1mm (meets the requirements).
square pads	The via diameter Dv ≤ 1/2 of the pad side length, and the remaining copper foil width on each side of the pad ≥ 0.1mm;
Example	The square pad has a side length of 0.3mm × 0.3mm, a maximum Dv of 0.15mm, and a remaining width of 0.075mm on each side (Dv needs to be reduced to 0.12mm, leaving 0.09mm).
Prohibition principle	Dv must never exceed the pad boundary (i.e., Dv > Dp), otherwise the via will be exposed outside the pad, and the solder will flow into the via during soldering, resulting in insufficient solder on the pad and a cold solder joint rate of over 10%.

2. Via diameter matching with component pins

The via diameter must be compatible with the component lead size to avoid the lead being unable to be inserted (for through-hole components) or insufficient solder fill (for surface-mount components).

Surface mount components	The via diameter Dv should be 0.05-0.1mm smaller than the component lead width (e.g., for a 0402 resistor with a lead width of 0.15mm, Dv = 0.1-0.12mm) to ensure that the solder can cover the lead and the via.
Plug-in components	The via diameter Dv is 0.05-0.1mm larger than the component lead diameter (e.g., if the lead diameter is 0.2mm, Dv=0.25-0.3mm) to facilitate lead insertion and ensure solder fill of the via.
Real-world examples	When designing the vias within the pads of the 0402 component, Dp=0.3mm and Dv=0.2mm (over 1/2 scale), the remaining copper foil width was only 0.05mm. During soldering, the solder could not fully cover the pins, resulting in a cold solder joint rate of 15%. After adjusting Dv to 0.12mm, the remaining width was 0.09mm, and the cold solder joint rate dropped to 1.2%.

The placement of pads and vias in the design should ensure that the vias are centered and avoid offset.

Via misalignment can lead to uneven copper foil distribution on the pads, with one side having too narrow a copper foil layer (<0.05mm). This can cause solder flow deviation during soldering. The core specifications are as follows:

1. Offset between via center and pad center

Offset ≤ 0.05mm (approximately 1/3 of the via diameter), ensuring that the difference in the width of the remaining copper foil on each side of the pad is ≤ 0.03mm;

Example: Dv=0.15mm, pad Dp=0.4mm. If the offset is 0.05mm, the remaining width on one side = (0.4-0.15)/2 -0.05=0.125-0.05=0.075mm, and the width on the other side = 0.125+0.05=0.175mm, a difference of 0.1mm (acceptable). If the offset is 0.08mm, the remaining width on one side is 0.045mm, which is out of tolerance.

For high-precision scenarios (such as RF signal layers): offset ≤ 0.03mm to avoid impedance abrupt changes caused by signal path asymmetry (0.05mm offset may result in impedance deviation exceeding 5%).

2. Minimum distance between via and pad edge

The minimum distance between the via edge and the pad edge should be ≥0.08mm to prevent the copper foil from breaking due to the via being too close to the pad edge (drilling during manufacturing can easily damage the pad).

Calculation method: Minimum distance = (pad size – via size) / 2 – offset;

Example: Dp=0.4mm, Dv=0.2mm, offset 0.03mm, minimum distance = (0.4-0.2)/2 -0.03=0.1-0.03=0.07mm (close to 0.08mm, the offset needs to be adjusted to 0.02mm, minimum distance 0.08mm).

solder pads, vias, and solder mask should avoid the solder mask affecting the soldering process.

Improper solder mask design can lead to “solder mask covering the pads” or “solder mask entering vias,” affecting solder wettability. The core specifications are as follows:

1. Weld resistance window size

The solder mask opening size for vias within the pads needs to be 0.1-0.2mm larger than the pad size (0.05-0.1mm larger on each side) to ensure that the solder mask does not cover the pads.

Example	The diameter of the circular pad Dp is 0.4mm, and the diameter of the solder mask opening is 0.4 + 0.2 = 0.6mm (0.1mm larger on each side).
prohibit	The window size should be less than or equal to the pad size; otherwise, the solder resist will cover the edge of the pad (0.05mm wide), and the solder will not be able to adhere during soldering, resulting in the defect of “insufficient exposed copper on the pad”.

2. Through-hole solder mask treatment

For vias that require solder filling: No solder resist needs to be applied inside the via (i.e., solder resist openings cover the via), ensuring that the solder can fill the via (fill rate ≥ 80%).

Vias that do not require solder filling: Solder resist can be applied inside the via (via plugging) to prevent solder from flowing into the via and causing insufficient solder on the pads. However, it is necessary to ensure that the solder resist filling is flat (protrusion ≤ 0.03mm) and does not affect component placement.

In pad and via design, copper foil connection specifications must ensure conductivity and heat dissipation.

The copper foil connection of vias within pads must meet the requirements of “low impedance and high heat dissipation”. The core specifications are as follows:

Copper foil thickness

The copper foil thickness of the pads should be ≥35μm (1oz). The copper foil around the vias should be completely covered without breaks or gaps (gap width ≤0.03mm) to avoid increasing the on-resistance (a gap of 0.05mm may increase the resistance by 20%).

heat dissipation copper foil

For vias in the pads of high-power components (such as LEDs and power resistors), heat dissipation copper foil (with an area ≥ twice the area of the pad) needs to be designed around the pads. Heat is conducted to the inner heat dissipation layer through the vias to prevent the components from overheating (e.g., for a 1W 0603 power resistor, the temperature exceeds 120℃ when the heat dissipation copper foil is insufficient, and drops to 85℃ after increasing it).

The design of vias within PCB pads requires “parameter quantification and strict adaptation.” The core is to control the size ratio, positional offset, and solder mask openings between the vias and pads to avoid design defects that could lead to subsequent soldering and signal problems.

Parameter matching reference for pad and via design

Pad vias penetrate the entire PCB layer and are suitable for scenarios requiring full-layer conductivity (such as power lines and general signal lines). The design should focus on the via diameter, pad size, and via spacing.

Hole diameter matching pad size	The via diameter should be determined based on the current carrying capacity requirements. For conventional signal vias, a diameter of 0.3-0.6mm is recommended, and the corresponding pad diameter should be 2-2.5 times the via diameter (e.g., a 0.4mm via diameter should be matched with a 0.8-1.0mm pad) to ensure that the solder can fully cover the pad during soldering and avoid cold solder joints. For high-current vias (carrying currents above 5A), the via diameter should be ≥1.0mm, and the pad diameter should be ≥2.0mm. At the same time, a “cloverleaf” pad design (4-6 small pads are set around the via) should be adopted to enhance heat dissipation and mechanical strength.
Layout rules	The distance between vias and component pads should be ≥0.5mm to prevent solder from flowing into the vias and causing short circuits during soldering; the distance between vias and board edges should be ≥1.0mm to prevent PCB edge cracking; the via spacing in high-density areas should be ≥0.8mm (center distance). If “staggered arrangement” is used (the position of adjacent layer vias is offset by more than 0.4mm), the spacing can be reduced to 0.6mm to increase wiring density.
Impedance control parameters	For high-frequency signal vias (frequency ≥ 1 GHz), impedance matching needs to be controlled. This is achieved by adjusting the via wall plating thickness (typically 20-30 μm, 30-40 μm for high-frequency scenarios) and the pad/anti-pad size (anti-pad diameter is 0.2-0.4 mm larger than the pad). For example, for a 50 Ω impedance via on an FR-4 substrate (dielectric constant 4.4), a 0.4 mm via diameter needs to be paired with a 0.8 mm pad and a 1.2 mm anti-pad to ensure signal reflection loss ≤ -15 dB.

Inner Layer Connectivity Optimization Reference in Pad and Buried Via Design

Buried vias exist only in the inner layers of a PCB (without penetrating the surface layer). They are suitable for scenarios where there is inter-layer conductivity and the surface layer routing space needs to be increased (such as the inner layer power distribution network of a multi-layer PCB). The design focus is on inner layer positioning and insulation of the via walls.

Inner layer positioning and dimensions	Buried vias need to be precisely positioned at the intersection of inner layer traces. The recommended via diameter is 0.2-0.5mm, and the inner layer pad size is 1.8-2 times the via diameter (e.g., a 0.3mm via diameter should be matched with a 0.54-0.6mm inner layer pad). The distance between the buried via and the inner layer traces should be ≥0.2mm to avoid damaging the inner layer traces during drilling.
Hole wall insulation treatment	After the buried via is drilled, it needs to be “insulated” by filling it with epoxy resin (filling depth ≥ 95% of the hole depth). After curing, it should be ground smooth before the inner layer circuitry is fabricated to prevent short circuits between the buried via and adjacent inner layer circuitry. The epoxy resin used for filling should be a high-temperature resistant type (Tg ≥ 150℃) to avoid softening and overflowing during subsequent soldering.
Layered structure adaptation	The buried vias must be compatible with the PCB stack-up structure. For example, in an 8-layer PCB, if it is necessary to achieve conductivity between 2-3 layers, the buried vias must be drilled and fabricated before laminating the 2-3 layers. If it is necessary to achieve conductivity between 4-5 layers, the vias must be laminated independently between the 4-5 layers and then laminated with other layers to ensure that the buried vias only penetrate the target inner layer and do not affect other layers.

Depth Control Reference in Pad and Blind Via Design

Blind vias penetrate only the surface and inner layers of the PCB (without penetrating the bottom layer). They are suitable for scenarios where the surface and inner layers are interconnected and the surface space needs to be minimized (such as bottom signal connections in BGA packages). The core design considerations are depth accuracy and interlayer alignment.

Depth to aperture ratio	The ratio of blind hole depth (distance from the surface to the inner target layer) to hole diameter must be ≤1:1.5. For example, for a blind hole with a diameter of 0.3mm, the maximum depth is 0.45mm. Exceeding this ratio will lead to drilling difficulties and excessive hole wall roughness (Ra>1.0μm). If a deeper blind hole is required (such as 0.6mm depth), a “stepped blind hole” design must be adopted (drilling in two stages, first drilling 0.3mm deep to the middle layer, and then drilling 0.3mm deep to the inner target layer) to ensure hole wall quality.
Interlayer alignment accuracy	The alignment deviation between upper and lower layers of blind vias must be ≤0.02mm. During the design phase, “alignment marks” (such as circular reference points with a diameter of 1.0mm) must be set on the PCB. During production, the alignment is calibrated using an X-ray positioning system. At the same time, the interlayer distance between blind vias and adjacent blind vias must be ≥0.3mm to prevent drill bit misalignment during drilling, which could lead to hole wall connection.
Surface treatment adaptation	The surface opening of blind vias must match the surface treatment process. For immersion gold processing, the immersion gold thickness inside the blind via must be ≥0.8μm (using the “pulse immersion gold” process to enhance the uniformity of the plating inside the via). For OSP processing, an OSP coating (0.2-0.5μm thick) must be applied inside the blind via to prevent oxidation of the copper foil inside the via, which would affect the reliability of the soldering.

Applications of different PCB vias

General Electronics	Standard vias and through-holes can handle everyday multi-layer wiring, stitching, and low-cost construction.
Mobile devices and wearable devices	Blind via PCB structures help avoid using fine-pitch BGAs without burning out layers, thus keeping the board thin while accommodating large batteries.
Aerospace/Medical	Embedded PCB connections keep the outer layers clean, facilitate the application of components and conformal coatings, and protect the inner layer connections.
5G and high-speed computing	Microvia PCB stacking (staggered or stacked) shortens the vertical transition and suppresses parasitic effects in dense HDI.
Power supply and lighting	An array of thermal vias beneath the regulator, MOSFET, and LED transfers heat to the plane, allowing the heatsink to truly function.

Summarize

designed into PCB pads are more than just holes; they are the robust architecture that enables modern hardware. From common through-hole vias to blind vias, buried vias, and microvias, a variety of PCB stacking structures allow you to integrate more functionality in a smaller space without sacrificing reliability. When extremely high density is required, such as BGA packages smaller than 0.8 mm, vias within pads can excel when combined with in-fill via PCB processes, ensuring strong solder adhesion and a flat pad. Even standard PCB pad via sizes must appear in the Bill of Materials (BOM): smaller apertures improve signal integrity and routing, but also increase costs and shorten production cycles. If you require extreme compactness, blind vias and buried vias enable true HDI layouts for mobile phones, wearable devices, and high-density IoT devices. In short, choosing the right pad via strategy depends half on design and half on manufacturing. If you want to reduce unexpected issues and improve yield , or if you need a manufacturer capable of producing PCBs in high volumes, please contact our team.