Comprehensive Guide to FPC Via Design

Vias are metallized via structures that penetrate the dielectric layers of an FPC (Flexible Printed Circuit) to achieve interlayer electrical interconnection. They include through-hole vias, blind vias, buried vias, and microvias. In engineering, they are used for interlayer signal and power connections in double-sided and multi-layer FPCs. The via diameter and pad size determine the wiring density. Vias located in bending areas can cause stress concentration and breakage of the copper foil, which is a major taboo in FPC reliability design.

FPC via design overview

Vias are a key structural element for interlayer interconnection in flexible printed circuits (FPCs). In flexible circuit boards, via design needs to balance electrical conductivity, mechanical reliability, and bending performance. Improper via design is one of the common causes of FPC failure.

FPC via type

Through Hole	This design, which penetrates all layers and has a aperture range of 0.15-0.5 mm, is the most commonly used, mature, and cost-effective.
Blind Via	From the outer layer to the inner layer, it is non-penetrating, with a hole diameter range of 0.1-0.2 mm. It is commonly used in HDI designs and requires laser drilling .
Buried Via	It is entirely in the inner layer, with a pore size ranging from 0.1 to 0.2 mm. It does not occupy the outer layer space, but it is highly complex to manufacture.

Via size specifications

parameter	Standard process	Precision craftsmanship
Minimum aperture	0.2 mm	0.1 mm
Pad diameter	Aperture +0.3mm	Aperture +0.2mm
Pad to Line Spacing	0.15 mm	0.10 mm
Hole-to-hole distance	0.5 mm	0.3 mm
Hole to plate edge	0.5 mm	0.3 mm

Via process

Mechanical drilling	Aperture ≥ 0.2 mm is suitable for through holes, but the hole walls may be rough. The advantage is lower cost.
Laser drilling	With a hole diameter ≥ 0.05 mm, it is suitable for micro-holes and blind holes. The hole walls are smooth after processing, and its advantage is high precision.
Electroplating filler	Copper-filled vias offer good heat dissipation and conductivity, making them suitable for thermal vias and stacked vias, but they have higher processing costs.

Key rules for vias and bends

• Vias are prohibited in bending areas: Vias are stress concentration points, and in bending areas, they can cause copper foil to crack.

• The distance between the through hole and the boundary of the bend area is ≥ 1 mm.

• Vias near the dynamic bending zone require special evaluation.

• Avoid placing vias near bends in densely populated areas.

Hot via design

Thermal vias are used for heat dissipation:

• Aperture 0.3-0.5 mm

• Hole spacing: 0.8-1.2 mm

• Copper paste or electroplating filler

• Placed below the heating element

• Connecting copper foil increases heat dissipation area

How is the aperture determined?

Conventional interconnect	0.2-0.3mm
Power Via	0.3-0.5mm
Hot via	0.3-0.5mm
HDI micropores	0.1-0.2mm
Connector through hole	According to connector specifications

Is the via in a safe zone?

Through hole distance to bend area	>1mm safety
Through hole distance to bend area	0.5-1mm requires evaluation
via in the bend area	prohibit
The dense area of vias is near the bend line.	Not recommended

Are the pad sizes sufficient?

Pad diameter	≥Aperture + 0.3mm is acceptable
Pad to Line Spacing	≥0.15mm is acceptable
Hole-to-hole distance	≥0.5mm is acceptable
Hole to plate edge	≥0.5mm is acceptable

Core Rules for Half-Hole Design on Plate Edge

1．Basic parameters

aperture	≥0.3mm (for independent half-holes, elliptical pads are recommended, and the width of the remaining pads on the board should be ≥0.3mm).
layout	The hole center should be aligned with the outline of the GM/GKO layer, with a deviation of ≤±0.05mm.
Gold finger design	Each pad is equipped with 2 vias (half-hole on the board edge + via inside the board), staggered by ≥0.3mm, to avoid a row layout (to prevent board breakage).

2．Key points of the process

Round the edge of the half hole (radius ≥ 0.1 mm) to eliminate burrs; the major axis of the elliptical pad is ≥ 0.6 mm and the minor axis is ≥ 0.4 mm.

Through-hole layout anti-breakage plate design

Prohibited items

• The vias should be arranged in rows (staggered vertically/horizontally by 0.3-0.5mm);

• Half-hole/window pads are located in the bend area (≥0.5mm from the center of the bend);

• The positioning hole is less than 0.5mm from the edge of the board (the edge of the positioning hole is ≥0.5mm from the board frame).

solder pads and solder mask

• The outer diameter of the through hole must be greater than or equal to the inner diameter plus 0.2 mm; the outer diameter of the insertion hole must be greater than or equal to the inner diameter plus 0.4 mm.

• Outer diameter of open area + 0.05-0.1mm.

• The vias must be completely covered by the covering film; partial opening is prohibited (to prevent oxidation and breakage).

Borehole layer definition

• Metallized Hole (PTH): Designed in the borehole layer, with a diameter tolerance of ±10%.

• (Non-metallized holes/grooves: designed on the GM/GKO layer, on the same layer as the board frame line, and no extraneous lines are allowed (to prevent omissions).

DFM Checklist

• Has the via type been labeled?

• Do the aperture and pad size meet the specifications ?

• Is the via in the bend area?

• Is the distance between the through hole and the bend area ≥ 1mm?

• Is the copper thickness of the via ≥20μm ?

• Has the blind via/buried via process been confirmed?

• Has the drilling descaling process been confirmed?

• Have the hot vias been filled with copper?

• Has 100% electrical testing been planned?

Common errors

The bending area is exposed through the hole	Vias are stress concentration points; when bent, the copper foil cracks at the via. Vias must be prohibited in the bending area.
Insufficient copper thickness in the hole	Fracture under thermal stress occurs when the copper hole diameter is less than 20μm, requiring confirmation of the electroplating process capability.
Via pads too small	Poor electroplating when the pad diameter is less than the hole diameter + 0.25 mm leads to interlayer open circuits.
Blind holes were not drilled to remove drilling debris.	Residual adhesive on the walls of laser blind holes, if not removed, will lead to interlayer insulation problems.
Hot vias without copper filler	Holes have high thermal resistance and poor heat dissipation; thermal vias should be filled with copper or copper paste.
Via offset not detected	Drilling misalignment caused a short circuit between the via and the wiring, requiring AOI inspection.

Design Reference for FPC Via Design in Practical Applications

In practical applications, via design requires comprehensive consideration of multiple factors, including electrical performance, thermal characteristics, mechanical reliability, and process feasibility. For example, in wearable devices, vias must ensure stable signal transmission while adapting to frequent bending mechanical environments; in automotive electronics, vias need to withstand greater temperature variations and vibration shocks; and in high-frequency applications, the electromagnetic characteristics of vias become a primary consideration. This multiphysics coupling analysis makes modern FPC via design a complex systems engineering project, requiring advanced simulation tools and extensive engineering experience for optimization.

Summarize

As electronic devices continue to evolve towards miniaturization and higher performance, FPC via technology is also constantly innovating. New microvia fabrication techniques, conductive materials, and high-density interconnect solutions are emerging, driving vias towards smaller sizes, higher reliability, and superior electrothermal performance. These technological advancements not only expand the application boundaries of FPCs but also provide more possibilities for the design of next-generation electronic devices, fully demonstrating the immense value of this tiny structure in modern electronic engineering. If you require high-volume FPC manufacturing, please contact Geyuan Electronics for assistance.